This invention relates generally to a method for forming thin film capacitors, and more particularly to such a method that includes forming the capacitors by multi-level dry processing techniques.
Integrated, low inductance capacitors are essential to the operation of high performance, very large scale integrated (VLSI) semiconductor packages. The integrated capacitors are typically part of a multi-layered ceramic (MLC) power stabilizing interposer structure containing through vias. In particular, high performance single chip module (SCM) and multi-chip module (MCM) packages need discrete capacitors in the nanofarad range which are typically placed very close to silicon chip microprocessors. Signal propagation characteristics of these packages can be further enhanced by placing thin film capacitors directly under the chip. This arrangement requires that the thin film capacitors be fabricated on the top side of an interposer substrate. For high permittivity, materials such as barium strontium titanate (BST) are typically used as dielectric materials, with platinum commonly used as a conductive metal, and barrier layers formed of metal nitrides The top surface metallurgy (TSM) i.e., the exterior interconnect features, are typically formed of conductive metals such as chromium, copper, nickel, gold, and alloys of such materials. Often, the top surface metallurgy is arranged to enable the C-4 (Controlled Collapse Chip Connection) solder joining of chips to the interposer.
In the fabrication of thin film capacitors, various layers of the structure must be patterned separately in a sequential manner. The number of photo-patterning steps needed for processing such devices depends on the number of layers required in the end structure or device. Conventional etching processes use photo resist patterns and different etchant baths, for example, aqua regia for platinum, hydrochloric acid for barium strontium titanate, and other strong acids for metal nitride barrier layers. Strong etchants adversely affect the bond between the resist material and the underlying layer, causing delamination during the etch process which, in turn, makes pattern delineation less precise and thus impacts the design, fidelity and quality of the manufactured structure. Also, the critical success of wet methods depends on the ability of specific etchants to only etch one layer without affecting the other layers of the structure. Furthermore, handling of such chemicals in a manufacturing environment requires additional environmental controls and handling precautions. In addition, wet processing chemicals used for etching may have undesirable effects on substrates.
The present invention is directed to overcoming the problems set forth above. It is desirable to have a dry processing method for forming vias through thin film capacitors that does not require the use of wet etchant solutions and baths. It is also desirable to have such a method in which dry processes, such as ion beam etching laser beam etching, and reactive ion etching in an appropriate reactive atmosphere, can be used in a specific sequence to form vias in thin film capacitor structures.